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Algorithmic Aspects of Vlsi Layout

Description

Discussing algorithmic aspects of VLSI layout, this text includes coverage of: issues in timing driven layout; LP formulation of global routeing and placement; Stockmeyer's floorplan optimization technique; the Manhattan and knock-knee routeing modes; and parallel algorithms for placement.

Keywords

VLSI cell placement graph Hypergraph Integar program formulation Circuit partitioning algorithms Routing problem Straight line embedding plane graph

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Algorithmic Aspects of Vlsi Layout.djvu

DJVU

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