Designing Embedded Processors

Trends in Designing SOCs Embedded Processors Extensible Processor SOC Design Distinction Challenges in Embedded Extensible Processor Code Segment Identification Extensible Instruction Generation Architectural Customization Selection NISC Technology NISC vs. ASIP NISC vs. VLIW NISC vs. Microcoded Architectures NISC vs. HLS Compilation Algorithm Power Optimizations in NISC Switching Capacitance Pipeline Structure Custom Datapath Design Synthesizing Instruction Sets Optimizing for Energy-Efficiency Effects of Bitwidth Variation MPSoC Synthesis Custom Processor Synthesis Hybrid Custom Instruction Co-Processor Synthesis Multiobjective Evolutionary Algorithm Heterogeneous Multiprocessor Synthesis Design Time Compression Run Time Code Compression Cache Trace Compression Cache Size Prediction Code Compression Code Compression Technique Embedded Memories Power Optimisation Strategies Partitioned Memory Compression Encoding Dynamic Voltage Scaling Dynamic Voltage Scaling Power Management in DRAM Layer Assignment Techniques Data Reuse Analysis Power Area and Time Trade-off Data Reuse Analysis High-Level Estimations MHLA Search Space QSDPCM DAB Wireless Receiver Execution Time Measurements Memory Bank Locality Low-Power Operating Modes Global Optimizations Dynamic Voltage Frequency Scaling Power-Aware Scheduling Static DVFS Scheduling Dynamic DVFS Scheduling EDF Scheduling Fixed-Priority Scheduling Cycle-Conserving Real-time DVFS Delay Models Genetic Task Mapping Algorithm Genetic Scheduling Algorithm Optimal Continuous Voltage Selection Optimal Discrete Voltage Selection Compilation Techniques for Power Energy Optimizing Compilers Compiler Research Directions DVFS Evaluation Strategy Compiler Support Remote Task Mapping Multi-Processors (MPSoC) Interconnection Woes Network-on-Chip (NoC) IP-based Methodology NoC Router Architecture Optimization Techniques for NoC NoC Router Architectures Power-Performance Modeling MESH Heterogeneous Performance Balance Reconfigurable Computing Dynamic Reconfiguration FPGA Reconfiguration